As the feature size of lithographic geometry for NAND flash chips is decreased, the number of electrons that can be used in storage may also be reduced, and assuring accurate information storage may become more challenging. Moreover, reductions in feature size may increase the risk of inter-cell interference. High-capacity NAND flash memory may achieve high density storage by using multi-level cells (two bits/cell for multi-level cell (MLC) or three bits/cell for triple level cell (TLC)) to store more than one bit per cell. Four levels or eight levels or more may be used. A large number of levels (and small voltage differences between levels) may result in a relatively low signal-to-noise ratio of the read channel, and a relatively high raw bit error rate (RBER). Error-correction code (ECC) (e.g., a low density parity check (LDPC) code) may be used to mitigate read errors.
The use of an LDPC code may involve reading the flash memory multiple times, which may degrade the performance of the flash memory. Thus, there is a need for a system and method for reading a flash memory multiple times, while providing good performance.